Buffer minimization in RTL synthesis from coarse-grained dataflow specification

Abstract- This paper concerns area-efficient automatic hardware architecture synthesis and its optimization from dataflow graph(DFG) specification for fast HW/SW cosynthesis. A node in a DFG represents a coarse grain computation block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from conventional behavioral synthesis and complicates the problem. In the proposed design methodology, arcs in DFG are synthesized to intermediate buffers to store the transient data samples between nodes by using either registers or memory. Since the buffer size is the major factor of hardware overhead in the synthesized architecture, we aim to reduce the buffer size by applying a shift buffering technique and a buffer sharing technique. Experiments with H.263 decoder subsystem demonstrate the proposed techniques reduce the buffer requirement by around 44 % to make the resultant hardware close to the hand-optimized hardware. I