Microcoded reconfigurable embedded processors

Abstract. It is well-known that the main disadvantages associated with recon-figurable hardware are long reconfiguration latencies, high opcode space requirements, and complex decoder hardware. To overcome these disadvantages, weuse microcode since it allows emulation of "complex " operations which are performed using a sequence of smaller and simpler operations. Microcode is used tocontrol the reconfiguration of the reconfigurable hardware, either online or offline, and the execution on the reconfigurable hardware. Due to the multitude ofmicrocodes and their sizes, it is not feasible to provide on-chip storage for all microcodes. Consequently, the loading of microcode into a limited on-chip storagefacility is becoming increasingly more important. In this paper, we present two methods of loading microcodes into such an on-chip storage facility. 1 Introduction Traditionally, embedded processor design was very much similar to microcontrollerdesign. This meant that for each targeted set of applications, an embedded processor was designed in specialized hardware (commonly referred to as Application SpecificIntegrated Circuits (ASICs)). In the early nineties, we were witnessing a shift in the embedded processor design approach fueled by the need for faster time-to-market. Thisresulted in the utilization of programmable processor cores that were augmented with specialized hardware units, which were still implemented in ASICs. This meant thattime-critical tasks were implemented in specialized hardware units while other less time-critical tasks were implemented in software to be run on the programmable pro-cessor core [1]. This approach allows a programmable processor core to be re-used for different sets of applications without redesigning it. This leaves only the specializedhardware units to be (re-)designed for the targeted set of applications