Improving cache power efficiency with an asymmetric set-associative cache

1 Introduction To attack the speed gap between processor and main memory, aggressive cache architectures are widely employed in current general purpose microprocessors. For example, Alpha 21264 [5] processor has a 64KB, 2-way set associative L1 data cache and an L1 instruction cache of the same size. Cache design is a trade-off of many factors including hit latency, miss rate, chip area and power consumption. Balancing all these factors results in complex designs