Non-uniform set-associative caches for power-aware embedded processors

Abstract. Power consumption is becoming one of the most important con-straints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes a simple technique to reduce the static energy due to subthresh-old leakage current. The key idea of our approach is to allow the ways within a cache to be accessed at different speeds and to place infrequently accessed data into the slow ways. We use dual-Vt technique to realize the non-uniform set-associative cache, and propose a simple replacement policy to reduce average access latency. Experimental results on 32-way set-associative caches demon-strate that any severe increase in clock cycles to execute application programs is not observed and significant static energy reduction can be achieved, result-ing in the improvement of energy-delay2 product.