Blocking and Non-blocking Assignments in Explicit and Implicit Style Verilog Synthesis

We show transformations that convert blocking assignments into non-blocking assignments. Such transformations are useful because the parallel-processing nature of hardware is more easily conceptualized and mapped to technology with non-blocking assignment. To validate our theory, we synthesized using Synopsys FPGA Express, which supports both blocking and non-blocking assignments. Some of these transformations apply to both explicit-(IEEE P1364.1 proposed RTL synthesis standard) and implicit- (multiple clocking events in an always block) style Verilog. The more complicated transformations apply only to implicit-style code. We also notice there is a one-clock-cycle mismatch between implicit-style synthesis and simulation, which is, in general, solvable only for non-blocking assignment. We avoid this mismatch by modifying our testbench. We feel the complexity of transforming blocking to non-blocking assignment as well as testbench mismatch justify our decision to implement only non-blocking assignment in our Verilog Implicit to One-hot (VITO) preprocessor. Explicit versus Implicit There are two styles of behavioral code that can be synthesized: implicit and explicit. Explicit-style code is more restrictive than implicit-style code in two main respects: explicit-style code prohibits the use of while or forever loops, and explicit-style code allows only one clocking-event expression per always block (which must occur at the top of the block). Explicit-style code is accepted by all synthesis vendors and is the basis of the proposed IEEE P1364.1 standard [5] for the so-called “Register Transfer Level Subset ” of Verilog. Implicit-style code [1, 6] relaxes these restrictions so that multiple clocking events as well as while and forever loops are allowed, provided that the clocking events are identical (shown as @(posedge sysclk) in the following examples) and each loop contains at leas