Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures

Increasing microprocessor vulnerability to soft errorsind))F by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unadaU ssed Previously proposed instruction-level redU(] nt execution, as a means of dzFF(zUx errors, su#ers from a severe performance loss ds to the resource shortage caused by the large number of redUFz nt instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (F S), 2) prioritizing primary instructions (PRI), and 3) early retiring of redUflR nt instructions (ERT), that enable transient-faultd etecting redzFF nt execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In adfl tion, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement