Reducing Coherence Overhead in Shared-Bus Multiprocessors

To reduce overhead of cache coherence enforcement in shared-bus multiprocessors, we propose a selfinvalidation technique as an extension to write-invalidate protocols in a shared-bus environment. The technique speculatively identifies cache blocks to be invalidated and dynamically determines when to invalidate them locally. We also consider enhancing our self-invalidation scheme by incorporating read snarfing, to reduce the cache misses due to incorrect prediction. We evaluate our self-invalidation scheme by simulating SPLASH-2 benchmark programs that exhibit various reference patterns, under a realistic shared-bus multiprocessor model. We observed considerable reduction of invalidations with an average of 71.6% over the base Illinois protocol for the benchmark programs studied. We also discuss the effectiveness and hardware complexity of self-invalidation and its enhancement with read snarfing in our extended protocol. Keywords: cache coherence, read snarfing, self-invalidation, share..