Hardware Support for Dynamic Access Ordering: Performance of Some Design Options

Hardware Support for Dynamic Access Ordering: Performance of Some Design Options Sally A. McKee Department of Computer Science University of Virginia Charlottesville, VA, 22903 mckee@virginia.edu Memory bandwidth is rapidly becoming the performance bottleneck in the application of high performance microprocessors to vector-like algorithms, including the "grand challenge " scientific problems. Caching is not the sole solution for these applications due to the poor temporal and spatial locality of their data accesses. Moreover, the nature of memories themselves has changed. Achieving greater bandwidth requires exploiting the characteristics of memory components "on the other side of the cache" --- they should not be treated as uniform access-time RAM. This paper describes the use of hardware-assisted access ordering on a uniprocessor system. Our technique combines compile-time detection of memory access patterns with a memory subsystem that decouples the order of requests generated by t..