An Analytic Model of SMC Performance

Memory bandwidth is becoming the limiting performance factor for many applications, particularly scientific computations. Access ordering is one technique that can help bridge the processor-memory performance gap. We are part of a team developing a combined hardware/software scheme for implementing access ordering dynamically at run-time. The hardware part of this solution is the Stream Memory Controller, or SMC. In order to validate the SMC concept, we have conducted numerous simulation experiments, the results of which are presented elsewhere. Here we develop an analytical model to bound SMC performance, and demonstrate that the simulation behavior of our dynamic access-ordering heuristics approaches that bound. An Analytic Model of SMC Performance Sally A. McKee Department of Computer Science University of Virginia Charlottesville, VA 22903 mckee@cs.virginia.edu An Analytic Model of SMC Performance 1 An Analytic Model of SMC Performance 1. Introduction The growing disparity be..