Performance analysis of multiprocessor interconnection networks using a burst-traffic model

This memory reference pattern is typical of several types of access in shared-memory systems. Cache-line fetches and prefetches, vectorregister loads and stores, even paging traffic can be represented in this way. In addition to issuing bursts of accesses, another characteristic Cedar shares with modern microprocessor-based systems is illustrated in Figure 2.2. The amount of local processing that occurs between bursts of accesses varies across a wide rage, but the average value is small compared to the maximum. A negative-exponentially distributed random variable, which is the result of a Poisson process [21], also shares this characteristic. This distribution is characteristic of repeated trials with constant probability and is often used to model real-world behavior of unpredictable systems. We choose to use such a distribution to determine the time which passes between the reception of one burst and the issuance of the next. Based on these two characteristics (bursts of accesses with Poisson inter-burst times) we develop our "burst-traffic" model. Three parameters determine the timing of accesses in the burst-traffic model. Figure 3.2 illustrates these parameters. The upper row of packets (headers only) represent the requests sent by a single processor during each burst. The lower row of packets (headers and data words) represent returning responses. The burst length (B) determines the number of packets issued by a processor during a burst. The access size (N d ) determines the number data flits in each response packet of burst. The total number of data flits accessed in a burst is the product of the burst length and access size. Because four flits are needed to represent one data word, the access size is equal to four times the number of data words returned by a r..