The Semantics of Behavioral VHDL'93 Descriptions

We present a rigorous but transparent semantic definition of VHDL'93 covering the complete signal behavior and time model including the various wait statements and signal assignment statements. We present a VHDL interpreter in the form of rules of a concurrent evolving algebra which faithfully reflects and supports the view given in the VHDL'93 standard language reference manual. 1 Introduction Approaching the definition of a formal semantics of the IEEE Std-1076 hardware description language VHDL'87 as well as of the new VHDL'93 1 [VHDL93] standard is of high interest for the synthesis and the formal verification of VHDL models. Borrione and Paillet [BoPa87] have done first investigations defining the semantics of a VHDL'87 subset in terms of a functional model. Further investigations can be found in [Sal92, SaBo93]. The definition of a subset of the VHDL'87 semantics in terms of Booyer-Moore Logic is presented by Read and Edwards in [ReEd94]. Wilsey [Wilsey90] defines the semantic..