This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecture that implements coherentsharedmemory through a combination of hardware and software mechanisms. For each block of memory, Alewife implements between zero and five coherence directory pointers in hardwareand allows software to handle requests when the pointers are exhausted. The software includes a flexible coherence interface that facilitates protocol software implementation. This interface is indispensable for conducting experiments and has proven important for implementing enhancements to the basic system. Simulations of a number of applications running on a complete system (with up to 256 processors) ...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis (Ph. D.)--University of Washington, 1997Two recent trends are affecting the design of medium-...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1993. Simultaneously published ...
Plentiful research has addressed low-complexity software-based shared-memory systems since the idea ...
Shared-memory architectures represent a class of parallel computer systems commonly used in the comm...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...
Traditionally, cache coherence in multiprocessors has been maintained in hardware. However, the cost...
In programming high performance applications, shared address-space platforms are preferable for fine...
PLATINUM is an operating system kernel with a novel memory management system for N on-Uniform Memory...
Abstract—Scalable distributed shared-memory architectures rely on coherence controllers on each proc...
This thesis describes and evaluates the effectiveness of four hardware mechanisms for software share...
Recent developments in shared-memory multiprocessor systems advocate using off-the-shelf hardware to...
This paper describes Shasta, a system that supports a shared address space in software on clusters o...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis (Ph. D.)--University of Washington, 1997Two recent trends are affecting the design of medium-...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1993. Simultaneously published ...
Plentiful research has addressed low-complexity software-based shared-memory systems since the idea ...
Shared-memory architectures represent a class of parallel computer systems commonly used in the comm...
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented ...
Traditionally, cache coherence in multiprocessors has been maintained in hardware. However, the cost...
In programming high performance applications, shared address-space platforms are preferable for fine...
PLATINUM is an operating system kernel with a novel memory management system for N on-Uniform Memory...
Abstract—Scalable distributed shared-memory architectures rely on coherence controllers on each proc...
This thesis describes and evaluates the effectiveness of four hardware mechanisms for software share...
Recent developments in shared-memory multiprocessor systems advocate using off-the-shelf hardware to...
This paper describes Shasta, a system that supports a shared address space in software on clusters o...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Thesis (Ph. D.)--University of Washington, 1997Two recent trends are affecting the design of medium-...
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a s...