Development of Compiler Design Techniques for Effective Code Optimisation and Code Generation

Abstract-- Many research groups have addressed code generation issues for a long time, and have achieved high code quality for regular architectures. However, the recent emergence of the electronics market that involves parallel processors constitutes a large pool of irregular architectures, for which standard techniques result in unsatisfying code quality. Lee, Lee et al. [LLHT00] focus on minimizing Hamming distances of subsequent instruction words in VLIW processors. They show that their formulation of poweroptimal instruction scheduling for basic blocks is NP-hard, and give a heuristic scheduling algorithm that is based on critical-path scheduling. They also show that for special multiissue VLIW architectures with multiple slots of the same type, the problem of selecting the right slot within the same lon