Accelerating Gate Matching in the Mapping Step Using Don't Cares

At the end of the logic synthesis, the technology mapping maps the Boolean function on physical cells. This step is based on a matching check, which complexity depends on the number of library cell inputs, and increases if don't cares are considered. We present a method based on fault analysis techniques, which uses a structural equivalent of the cell. This method allows to prune dramatically the design space, and directly derives the input phase. The experimental results show a gain of 2 to 3 orders of magnitude relative to the conventional ones, and behaves almost linearly with the complexity. Keywords Logic synthesis, Boolean matching, technology mapping, ROBDD. 1 INTRODUCTION The technology mapping is the last and decisive step of the logic synthesis : it transforms a multi-level logic representation into an interconnection of components which are instances of cells of a given library. The mapping may be done on various technologies or implementation styles : standard cells, FPG..