We present here the Controlling Value Boolean Matching based on fault analysis. The problem is to match a Boolean function with don't cares on library cells under arbitrary input permutations and/or input-output phase assignments. Most of the library cells can be represented by tree structure circuits. The approach presented here is suitable for these structures and computes the Boolean matching better than the structural matching used in SIS. It can handle library cells with a general topology and reconvergent paths. The benchmark test shows that the Controlling Value Boolean Matching can be as faster as the structural matching used in SIS
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
[[abstract]]This paper presents a very efficient Boolean logic optimization method. The boolean opti...
Application of the Boolean difference concept towards generation of tests for combinational and to s...
We present here the Controlling Value Boolean Matching based on fault analysis. The problem is to ma...
At the end of the logic synthesis, the technology mapping maps the Boolean function on physical cell...
Boolean matching is to check the equivalence of two func-tions under input permutation and input/out...
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
When binding a logic network to a set of cells, a fundamental problem is recognizing whether a cell ...
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
This paper proposes a fast algorithm for Boolean matching of completely specified Boolean functions....
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
Boolean matching is a powerful technique that has been used in technology mapping to overcome the li...
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
[[abstract]]This paper presents a very efficient Boolean logic optimization method. The boolean opti...
Application of the Boolean difference concept towards generation of tests for combinational and to s...
We present here the Controlling Value Boolean Matching based on fault analysis. The problem is to ma...
At the end of the logic synthesis, the technology mapping maps the Boolean function on physical cell...
Boolean matching is to check the equivalence of two func-tions under input permutation and input/out...
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
When binding a logic network to a set of cells, a fundamental problem is recognizing whether a cell ...
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
This paper proposes a fast algorithm for Boolean matching of completely specified Boolean functions....
[[abstract]]Boolean matching is to check the equivalence of two functions under input permutation an...
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
Boolean matching is a powerful technique that has been used in technology mapping to overcome the li...
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
A method for error correction in integrated circuit (IC) implementations of Boolean functions is des...
[[abstract]]This paper presents a very efficient Boolean logic optimization method. The boolean opti...
Application of the Boolean difference concept towards generation of tests for combinational and to s...