Logic-In-Memory Architecture For Min/Max Search

Algorithms for data-analytics executed on classical Von Neumann architectures proved highly energy inefficient. In- Memory Computing have been indicated as a practical solution to improve speed and to reduce power consumption. This work introduces a new memory architecture that extends the use of bit-wise logic operations to a more complex itera- tive algorithm, i.e., search of minimum/maximum values across bulk data. Such new design preserves all the characteristics of architectures for minimum/maximum detection, achieving high performance and low power consumption. It serves both as a local memory, and as an acceleration engine. It can be implemented with MOS transistors or with emerging devices. A novel imple- mentation of the minimum/maximum search algorithm has been tailored to fit the internal organization of the proposed memory architecture. A parametric analysis conducted on a 28nm FDSOI CMOS technology highlights remarkable results, with an energy consumption for single bit as low as 0.09fJ and a maximum operating frequency of 2GHz