ISA and Hardware Design for a Pipelined CIM-tile

Conventional Von Neumann machines inherently separate the processing units from the memory units. This architecture thus requires that data is transferred from the memory units to the processing units for performing computation, and results that should be stored are required to be transferred back to the memory units. Fast technological advances for processing speed have led to processors out-growing the speed at which data can be retrieved from the memory, meaning the bandwidth between the memory and the processor starts to bottleneck the system. This phenomenon is known as the Von Neumann bottleneck. Modern computer architectures utilize for example hierarchical memory architectures and pre-fetching schemes to alleviate the Von Neumann bottleneck. However, these methods do not succeed in fully removing the bottleneck. Furthermore, the energy required to retrieve data from the memory is several orders of magnitude higher than the energy required for a single operation within the processor. There is a clear need for a new computing paradigm to further progress modern computer architectures. This thesis aims to progress work on a novel in-memory computation architecture by contributing towards the instruction set definition and hardware implementation of the architecture. Simulation results and a proof-of-concept hardware implementation have been used to investigate the power consumption, energy consumption and latency of the designed digital circuitry. These characteristics are found to not impose any road-blocks towards progressing the architecture to new levels in future works. This thesis is part of the overarching MNEMOSENE project of which, among many others, the Delft University of Technology is a parter