In this brief, we propose local automatic rate adjustment in network-on-chips (NoC) (LAURA-NoC), a NoC with a distributed approach to dynamic voltage and frequency scaling (DVFS). The utilization of the switch buffers is used in a local feedback loop to automatically determine the appropriate clock frequency and voltage that allow the switch to sustain the rate at its input ports, without a global controller. The DVFS controller is simple and uses 2 voltage and 16 frequency values. We report a significant power saving compared to a global DVFS approach in a 45-nm CMOS technology, 33% on average over four realistic video applications
International audienceMany Processor Systems-on-Chip (MPSoC) have become tremendously complex system...
Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong...
Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitati...
Network-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but...
Abstract—In chip design today and for a foreseeable future, on-chip communication is not only a perf...
Power consumption remains one of the most important design objectives for network-on-chip (NoC) base...
We analyze the power-delay trade-off in a Network-on-Chip (NoC) under three Dynamic Voltage and Freq...
possible, but may result in an intolerable increase of network delay. We examined two DVFS policies,...
Previously, research and design of Network-on-Chip (NoC) paradigms where mainly focused on improving...
Dynamic Voltage and Frequency Scaling (DVFS) can be a very effective power management strategy not o...
A modern System-on-Chip (SoC) contains processor cores, application-specific process- ing elements, ...
Abstract—The use of power management techniques is mandatory in embedded devices, which must provide...
To effectively manage power in Globally-Asynchronous Locally-Synchronous (GALS) systems with many in...
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have becom...
Networks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of...
International audienceMany Processor Systems-on-Chip (MPSoC) have become tremendously complex system...
Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong...
Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitati...
Network-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but...
Abstract—In chip design today and for a foreseeable future, on-chip communication is not only a perf...
Power consumption remains one of the most important design objectives for network-on-chip (NoC) base...
We analyze the power-delay trade-off in a Network-on-Chip (NoC) under three Dynamic Voltage and Freq...
possible, but may result in an intolerable increase of network delay. We examined two DVFS policies,...
Previously, research and design of Network-on-Chip (NoC) paradigms where mainly focused on improving...
Dynamic Voltage and Frequency Scaling (DVFS) can be a very effective power management strategy not o...
A modern System-on-Chip (SoC) contains processor cores, application-specific process- ing elements, ...
Abstract—The use of power management techniques is mandatory in embedded devices, which must provide...
To effectively manage power in Globally-Asynchronous Locally-Synchronous (GALS) systems with many in...
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have becom...
Networks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of...
International audienceMany Processor Systems-on-Chip (MPSoC) have become tremendously complex system...
Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong...
Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitati...