We analyze the power-delay trade-off in a Network-on-Chip (NoC) under three Dynamic Voltage and Frequency Scaling (DVFS) policies. The first rate-based policy sets frequency and voltage of the NoC to the minimum value that allows to sustain the injection rate without reaching saturation. The second queue-based policy uses a feedback-loop approach to throttle the NoC frequency and voltage such that the average backlog of the injection queues tracks a target value. The third delay-based policy uses a closed- loop strategy that targets a given NoC end-to-end average delay. We first show that, despite the different mechanism and implementation, both rate-based and queue-based policies obtain very similar results in terms of power and delay, and...
On-chip networks (NoCs) promise to become an efficient communication infrastructure for multi-core a...
As Networks-on-Chip (NoCs) continue to consume a large frac-tion of the total chip power budget, dyn...
Abstract— Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for cu...
We analyze the power-delay trade-off in a Network-on-Chip (NoC) under three Dynamic Voltage and Freq...
possible, but may result in an intolerable increase of network delay. We examined two DVFS policies,...
Abstract—Power consumption remains one of the most impor-tant design objectives for network-on-chip ...
Networks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of...
Dynamic Voltage and Frequency Scaling (DVFS) can be a very effective power management strategy not o...
Abstract— Network-on-Chip (NoC) are considered the promi- nent interconnection solution for current...
Abstract—In chip design today and for a foreseeable future, on-chip communication is not only a perf...
Network-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but...
Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multi...
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have becom...
Previously, research and design of Network-on-Chip (NoC) paradigms where mainly focused on improving...
In this brief, we propose local automatic rate adjustment in network-on-chips (NoC) (LAURA-NoC), a N...
On-chip networks (NoCs) promise to become an efficient communication infrastructure for multi-core a...
As Networks-on-Chip (NoCs) continue to consume a large frac-tion of the total chip power budget, dyn...
Abstract— Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for cu...
We analyze the power-delay trade-off in a Network-on-Chip (NoC) under three Dynamic Voltage and Freq...
possible, but may result in an intolerable increase of network delay. We examined two DVFS policies,...
Abstract—Power consumption remains one of the most impor-tant design objectives for network-on-chip ...
Networks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of...
Dynamic Voltage and Frequency Scaling (DVFS) can be a very effective power management strategy not o...
Abstract— Network-on-Chip (NoC) are considered the promi- nent interconnection solution for current...
Abstract—In chip design today and for a foreseeable future, on-chip communication is not only a perf...
Network-on-Chip (NoC) is the high-performance and scalable alternative to the old-fashioned bus, but...
Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multi...
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have becom...
Previously, research and design of Network-on-Chip (NoC) paradigms where mainly focused on improving...
In this brief, we propose local automatic rate adjustment in network-on-chips (NoC) (LAURA-NoC), a N...
On-chip networks (NoCs) promise to become an efficient communication infrastructure for multi-core a...
As Networks-on-Chip (NoCs) continue to consume a large frac-tion of the total chip power budget, dyn...
Abstract— Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for cu...