Implementation of a power efficient synthetic aperture radar back projection algorithm on FPGAs using OpenCL

In this thesis, an implementation of a Synthetic Aperture Radar (SAR) back projection algorithm onto a Field-Programmable Gate Array (FPGA) device using Open Computing Language (OpenCL) is developed. SAR back projection is a method to form a high-resolution terrain image from radar data. SAR is used in many applications such as Geographic Information Systems (GIS), crop classification, oceanography, and much more. FPGA devices are normally written in a Hardware Description Language (HDL) to create highly parallel and optimized solutions. The FPGA device solution in this thesis is written in OpenCL, an open-source framework for heterogeneous computing devices including CPUs, GPUs, DSPs, and FPGAs. OpenCL provides a new method for programming FPGA devices using a familiar programming environment. OpenCL programming follows the C99 Standard and provides support for devices with parallel computing capabilities and leverages these capabilities in order to provide an optimized solution. A parallel implementation of a SAR back projection algorithm on FPGA is presented here and is profiled for timing, accuracy, and logic utilization to compare performance against CPU and GPU based design implementations. The presented OpenCL and FPGA back projection solution provides a throughput that is 18.7 and 2.2 times efficient in terms of power compared to CPU and GPU solutions