An OpenCL pipeline implementation on Intel FPGA for 3D backprojection

International audience3D back-projector computation is a time-consuming task, and hardware accelerators are used in order to speedup this algorithm. We propose a pipeline implementation of the 3D back-projection algorithm on a high-end FPGA using Intel FPGA SDK for OpenCL while presenting some optimization metrics for task par-allelism. Compared to a non-optimized version on Arria 10, we achieved a speedup of 23 regarding execution time, by applying these techniques properly. We then compared these results with a low-end FPGA, CPU and GPU in terms of execution time and energy efficiency. Index Terms-Algorithm architecture co-design, Intel FPGA SDK for OpenCL, hardware acceleration, FPGA, Computed Tomography