Design of a hardware efficient key generation algorithm with a VHDL implementation

The design and implementation of a key-generation algorithm will be discussed. The steps in the procedure consist of choosing a baseline algorithm for comparison, designing a new algorithm, testing and comparing the algorithms using C language programs, and then implementing the new algorithm using VHDL. The final result of testing the algorithm implemented in VHDL will be compared to the original results obtained from the C program implementing the new algorithm. C language programs of the chosen algorithms will be developed to verify their similarity and functionality. The results will be used to decide if the new algorithm selected for implementation is sufficiently robust, and similar in functionality to the baseline algorithm. After the algorithm is selected, it will be implemented in a hardware description language. This will be done for purposes of demonstrating top down design and hardware efficiency. This process will involve the steps of moving the design from an abstract algorithmic view, to a high level (behavioral) hardware description, and then to a low level (structural) description. This process will illustrate the details of moving the design from a theoretical level to a practical implementation level