Efficient VHDL models for various PLD architectures

VHDL is a flexible language for programming PLDs (Programmable Logic Devices) but the way it is synthesized for different architectures varies. Since there are several types of PLDs and several synthesis tools, it is very important for the designer to know which VHDL model to use for a particular architecture in order to achieve maximum efficiency. The term efficiency refers to a good use of resources that result to a denser fit of the logic design into the PLD with a minimum implementation delay. The choice of the VHDL model also depends on the application and the expectations of the designer. Based on the information from several PLD architectures, this thesis points out the maximum efficiency models for each architecture in different aspects of VHDL programming and sequential logic applications. The architectures that the study is focused on, are the Altera MAX family and the Cypress MAX, Flash and CY7C33x families