Energy constrained processing poses a number of challenges that have resulted in tremendous innovations over the past decade. Shrinking supply voltages and limited clock speeds have placed an emphasis on processing efficiency over the raw throughput of a processor. One of the approaches to increase processing efficiency is to use parallel processing with slower, lower resolution processing elements. By utilizing this parallel approach, power consumption can be decreased while maintaining data throughput relative to other more power-hungry architectures.;This low resolution / parallel architecture has direct application in the analog as well as the digital domain. Indeed, research shows that as the resolution of a signal processor falls belo...