IMPLEMENTATION OF HIGH-SPEED MULTIPLIER FILTERS USING A MODIFIED NON RECURSIVE COMMON DADA MULTIPLIER

A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis (Ayman.A et al (2001)). Many current DSP applications are targeted at portable, battery-operated systems, so that power dissipation becomes one of the primary design constraints. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. In this project two different multipliers are designed which are array multiplier and modified dada multiplier along with the combination of truncated multiplier. The comparison is carried out using the EDA tool XILINX ISE 12.3i by developing the RTL (Register Transfer Level) using the VERILOG HDL