A High Speed 16*16 Multiplier Based On Urdhva Tiryakbhyam Sutra

It is an ancient methodology of Indian mathematics as it contains a 16 SUTRAS (formulae). A high speed complex 16 *16 multiplier design by using urdhva tiryakbhyam sutra is presented in this paper. By using this sutra the partial products and sums are generated in one step which reduces the design of architecture in processor’s. By using this sutra we can reduce the time with high extent when compare to array and booth multiplier. It can be implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT) filtering and in microprocessors. By using this method we reduce the propagation delay in comparison with array based architecture and parallel adder based implementation which are most commonly used architectures .The main parameters of this paper is propagation delay and dynamic power consumption were calculated and found reduced