Modelling e verification language testbenches in UML 2.0 with theme and marte

This document presents a metamodel for the e Hardware Verification Language through example. The e metamodel is captured as a UML 2 profile (UML\u27s mechanism for lightweight extension). Stereotypes from this profile can be used at the modeling level as annotations on models of hardware verification testbenches. This document is organised into sections corresponding to the main constructs of the Hardware Verification Language. For each of these constructs we present: 1) a snippet of code showing their usage; 2) a UML model showing the profile; 3) a sample model annotated with the stereotypes from the profile (corresponding to the code snippet); 4) and an excerpt from the XPAND code generation templates that converts the UML model back into e source code. This document concludes with an overview of the specific extensions to the use of Theme/UML required to accommodate the aspect- oriented constructs in e.SF