A model-driven validation & verification environment for embedded systems
- A. Gargantini
- E. Riccobene
- P. Scandurra
Publication date
January 2008
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
This paper presents a validation and verification tool component, based on the Abstract State Machine formal method, that we are developing to support high level formal analysis of embedded system model-driven design. This component is integrated into a model-driven environment for HW/SW co-design that provides a graphical high-level representation of HW and SW components by means of UML profiles for SystemC/multi-thread C, and allows C/C++/SystemC code generation/back-annotation from/to graphical UML models
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