Scalable virtual memory via tailored and larger page sizes

Main memory capacity continues to soar, resulting in TLB misses becoming an increasingly significant performance bottleneck. The 4KB default minimum page size in architectures like x86 is decades old and hampers future growth potential. Current coarse grained page sizes, the solution from Intel, ARM, and others, have not helped enough. I propose Tailored Page Sizes on top of a Larger Base Page Size (TPS+). TPS+ allows pages of size 2 [superscript n], for all n greater than the minimum page size. TPS+ means one page table entry (PTE) for each large contiguous virtual memory space mapped to an equivalent-sized large contiguous physical frame. To make this work in a clean, seamless way, I suggest small changes to the ISA, the microarchitecture, and the O/S allocation operation. The result: TPS+ can eliminate more than 99% of all TLB misses and page walk memory accesses across a variety of SPEC17 and big data memory intensive benchmarks, yielding 59.7% average performance improvement in virtualized execution scenarios.Electrical and Computer Engineerin