Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main challenge in SPM design is to optimally map memory locations to scratchpad locations. This paper describes an algorithm to solve such a mapping problem by means of Dynamic Programming applied to a synthesizable hardware architecture. The algorithm works by mapping segments of external memory to physically partitioned banks of an on-chip SPM; this architecture provides significant energy savings. The algorithm does not require any user-set bound on the number of partitions and takes into account partitioning overhead. Improving on previous solutions, execution ti...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution w...
Many programmable embedded systems feature low power processors coupled with fast compiler controlle...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, ...
In this paper, we propose a fully automatic dynamic scratch-pad memory (SPM) management technique fo...
Abstract—We propose a code scratchpad memory (SPM) management technique with demand paging for embed...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
Memory-processor integration offers new opportunities for reducing the energy of a system. In the ca...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution w...
Many programmable embedded systems feature low power processors coupled with fast compiler controlle...
In order to meet the requirements concerning both performance and energy consumption in embedded sy...
Nowadays, many embedded processors include in their architecture on-chip static memories, so called ...
<p>An increasing number of processor architectures support scratch-pad memory - software manag...
In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, ...
In this paper, we propose a fully automatic dynamic scratch-pad memory (SPM) management technique fo...
Abstract—We propose a code scratchpad memory (SPM) management technique with demand paging for embed...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the dif...
Memory-processor integration offers new opportunities for reducing the energy of a system. In the ca...
Partitioning a memory into multiple blocks that can be independently accessed is a widely used techn...
This paper presents a dynamic scratchpad memory (SPM) code allocation technique for embedded systems...
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performan...
Abstract—Code repositioning is a well-known method of reducing inefficient off-chip memory accesses ...