輕量型微控器之微架構設計 及其在FPGA上之自適電壓調整實作;Microarchitecture Design of a Lightweight MCU and its AVS Implementation on FPGA

[[abstract]]以重複取樣 （Double Sampling; DS）或抖動偵測 （Transition Detection; TD）為基礎之前瞻臆測 （Speculative Lookahead; SL）技術已被證明在單純的資料路徑設計中優於傳統的Razor原位時序錯誤偵測器 （In-Situ Timing Fault Detector）設計。本論文則進一步探索其在微控制器設計之優勢。首先，我們實作目前最熱門的ARM Cortex M0+微控制器資料路徑，並分別加入Razor、SL和SL/TD三種原位時序錯誤偵測器。由於SL及SL/TD使用雙套資料路徑避免傳統Razor之短路徑 （Short Path）問題，在28奈米製程下可操作在5.75ns的設計，SL比Razor多用了18.8%之晶片面積，而SL/TD只有此設計比Razor少用了1.2%之晶片面積，在其他設計就會多用，但皆可分別省下37.1%和33.7%之功耗。另外本論文亦將含有原位時序錯誤偵測器之ARM Cortex M0+微控制器實作於可調整電壓之FPGA設計平台。以設計軟體估算之時脈的即時JPEG解碼應用可降低21.0%操作電壓，省下44.1%功耗。 Double sampling (DS)- or transition detection (TD)- based speculative lookahead has been proved to have better performance than traditional Razor-like in-situ timing fault detectors in simple datapath designs. In this paper, we further explore SL’s and SL/TD’s superiority in microcontroller datapaths. First, we have designed and implemented ARM Cortex M0+ datapaths, which is the most popular in embedded systems and incorporate Razor, SL and SL/TD in the datapaths for comparison. Due to the duplicated datapaths in SL and SL/TD, 18.8% area overheads and 1.2% area decreases exist in 28nm CMOS compared with that equipped with Razor. However, SL and SL/TD have 37.1% and 33.7% power reduction respectively. Finally, the ARM Cortex M0+ datapaths has been implemented on an FPGA platform that supports dynamic voltage scaling. The supply voltage and power consumption can be reduced by 21.0% and 44.1% respectively for real-time JPEG decoding