High-Level Synthesis Oriented Restructuring of Functions with While Loops

The usage of high-level synthesis (HLS) tools for FPGAs has increased significantly over the last years since they matured and allow software programmers to take advantage of reconfigurable hardware technology. Most HLS tools employ methods to optimize for loops, e. g. by unrolling or pipelining them. But there is hardly any work on the optimization of while loops. This comes at no surprise since most while loops have loop-carried dependences involving the loop condition which result in large recurrence cycles in the dataflow graphs. Therefore typical while loops cannot be parallelized or pipelined. We propose a novel transformation which allows to optimize while loops nested within a for loop. By interchanging the two loops, it is possible to pipeline (and thereby parallelize) the inner loop, resulting in a reduced execution time. We present two case studies on different hardware platforms and show the speedup factors - compared to a host processor and to an unoptimized hardware implementation - achieved by our while loop optimization method