FPGA implementation of congestion control routers in high speed networks

Receiving large number of data packets at different baud rates and different sizes at gateways in high-speed network routers may lead to a congestion problem and force the gateway to drop some packets. Several algorithms have been developed to control this problem. Among them the Random Early Detection (RED) algorithm is the most commonly used in several existing routers. It has been recommend by IETF (Internet Engineering Task Force) for next generation Internet gateways. In this thesis, a 10Gbps FPGA implementation of a modified version of the RED algorithm is proposed. This is achieved by enhancing the original RED algorithm in one hand, and by developing several hardware approximations of the arithmetic operations used in the algorithm in the other hand. The objective is to lower the risk of the global synchronization by reducing the number of packet drops and packet queuing time. The proposed algorithm and its implementation are validated through intensive VHDL simulations. Also, a comparison with the previous algorithm is conducted in order to show that our modified algorithm outperforms the original one in terms of packets drops