Implementing Reconfigurable Packet Matchers on Field-programmable Gate Arrays

In networking applications, packets of data can be sorted and filtered using a set of rules. Historically, this matching was done using conventional processors. As network speeds grow faster, the need for specialized circuitry to process these packets increases. Field Programmable Gate Arrays (FPGAs) are a technology that allows a user to create custom circuitry that can be changed to suit the application. Using FPGAs, this work looks to evaluate two approaches to performing packet classification at high-speed line rates of 10 Gbits/s and higher, with a 10% per 10 minute turnover in the ruleset. The first approach utilizes next-gen memory to store a million-entry ruleset; the second approach exploits a real-time partial reconfiguration of FPGAs to reprogram the FPGA circuitry with a variety of matching schemas. The two approaches are then compared to other FPGA-based systems, in terms of performance, rule density, and ease of updates.M.A.S.2021-11-30 00:00:0