Instruction Set Simulator for Transport Triggered Architectures

Due to specific requirements of some of embedded system applications, general purpose processors are usually not the most optimal ones for the task at hand. Thus, there is a need for application-specific processors, which are tailored for the application and requirements at hand. However, processor design is a demanding task. Therefore, the processor design flow needs to be automated as completely as possible. TTA Codesign Environment (TCE) is a toolset that provides a semi-automated processor design flow, which includes "design space exploration", which is a process that helps to find an optimal processor architecture for the given application semiautomatically. The processor paradigm utilized in TCE design flow is called transport triggered architecture (TTA). TTA is a relatively simple and highly modularized processor architecture which allows easy customization. One of the leading ideas of TTA is to move complexity from the processor hardware to the compiler. Consequently, the most complicated tool in TCE is the compiler. Instruction set simulation is mainly needed in verifying the compiler output and in design space exploration. The project completed for this thesis consisted of design, implementation, and verification of an instruction set simulator for TCE. The thesis describes the main requirements and most important software design decisions of the TCE instruction set simulator. In addition, the verification of simulation correctness is described and performance benchmarks are presented. Finally, several improvement ideas and brief plans for implementing them are presented. /Kir1