International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cache side channel attacks (CSCAs) over past few years. In this paper, we present a novel technique to detect CSCAs on Intel's x86 architecture. The proposed technique comprises of multiple machine learning models that use real-time behavioral data of concurrent processes collected through Hardware Performance Counters (HPCs). In this work, we demonstrate that machine learning models, when coupled with intelligent performance monitoring of concurrent processes at hardware-level, can be used in security for early-stage detection of high precision and stealthier CSCAs. We provide extensive experiments with four variants of the state-of-the-art CSCA...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceThis paper presents a run-time detection mechanism for access-driven cache-bas...
International audienceThis paper presents a run-time detection mechanism for access-driven cache-bas...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceThis paper presents a run-time detection mechanism for access-driven cache-bas...
International audienceThis paper presents a run-time detection mechanism for access-driven cache-bas...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceIntel's x86 architecture has been exposed to high resolution and stealthy cach...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceThis paper presents experimental evaluation and comparative analysis on the us...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceWe present a novel run-time detection approach for cache-based side channel at...
International audienceThis paper presents a run-time detection mechanism for access-driven cache-bas...
International audienceThis paper presents a run-time detection mechanism for access-driven cache-bas...