Designing single layer counter in quantum-dot cellular automata with energy dissipation analysis

Quantum-dot cellular automata is a promising nanotechnology and a possible alternative to complementary metal-oxide-semiconductor (CMOS) transistors. Nowadays, several sequential and combinational logic circuits have been designed and implemented using QCA nanotechnology. However the impact of energy dissipation constraint is still unobserved while the forming complex QCA circuits. This paper presents energy-efficient memory cell (JK flip-flop) and single layer counter circuit using QCA. Moreover, comprehensive energy consumption analysis of the proposed design along with structural comparison is performed over the state-of-the-art QCA memory cells. Experimental results show the computational supremacy of the proposed design in terms of cell counts, space intricacy, wire crossing and time delays. QCADesigner and QCAPro software tools are used for verifying the circuit functionality and estimating the energy dissipation of the proposed designs. Keywords: Quantum-dot cellular automata, QCA counter, JK flip-flop, Energy dissipatio