A D-Band Keyable High Efficiency Frequency Quadrupler

A D-band frequency quadrupler consisting of two cascaded push-push doublers is designed and manufactured in a 0.25 mu m InP DHBT technology. Each doubler has a Marchand balun implemented by broadside-coupled transmission lines, folded in a rectangular shape. The second balun, operating at a half of output frequency, is located inside of the first one for minimizing the chip size. The frequency quadrupler with a dc power consumption of 47 mW has a maximum conversion gain of 2 dB, and exhibits 12 to 25 dBc rejection ratio of the undesired first to fifth harmonics in the frequency range from 110 to 130 GHz. The quadrupler demonstrates a power efficiency of 10%, which is the highest among published quadruplers, as well as the highest conversion gain and an output power of 5 similar to 7 dBm without using power amplifiers. The chip size is 0.77 mm(2). By switching a cascode transistor, the quadrupler can also be used as an on-off keying modulator