High DC-to-RF Efficiency E-band Frequency Quadrupler Using Phase-Controlled Push-Push Structure in 28-nm FD-SOI CMOS

In general, a frequency multiplier provides better phase noise performance than fundamental oscillators at mm-wave frequencies. However, one of the drawbacks of higher order frequency multipliers is poor energy efficiency due to the use of multiple stages and driver amplifiers between multipliers. Here, we present a highly efficient 63.4 to 72.4-GHz frequency quadrupler that is based on the phase-controlled push-push (PCPP) structure in 28-nm FD-SOI CMOS. A single PCPP stage directly generates the fourth harmonic with good odd-harmonic suppression. In addition, due to push-push operation with low gate bias in the PCPP stack, the PCPP structure can provide higher energy efficiency. The fabricated quadrupler provided 11.4% peak DC-to-RF efficiency with 17-mW DC power consumption. Peak output power of the fourth harmonic was measured to be 2.9 dBm with a 9.9-dBm fundamental input signal at 65.6 GHz. The measured second-harmonic suppression was 38.6 dBc.1