A number of tasks in computer-aided analysis of combinational circuits, including test pattern generation, timing analysis, delay fault testing and logic verification, can be viewed as particular formulations of the satisfiability problem (SAT). The first purpose of this dissertation is to describe a configurable search-based algorithm for SAT that can be used for implementing different circuit analysis tools. Several methods for reducing the amount of search are detailed and integrated into a general algorithmic framework for solving SAT. Special emphasis is given to the description of methods for diagnosing the causes of conflicts that may be identified while searching for a solution to each instance of SAT. These methods allow the implem...
Consideration was given to the problem of time verification of the combinational circuits, namely, t...
Test Pattern Generation (TPG) for sequential and/or 3-state circuits involves two important aspects ...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
A powerful combinational path sensitization engine is required for the efficient implementation of t...
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds...
[[abstract]]Automatic test pattern generation (ATPG) for path delay faults is an essential tool for ...
The new test pattern generation system for path delay faults in combinational logic circuits conside...
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability o...
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel tech...
Abstract—Increasing speed and decreasing gate sizes make it necessary to test the correct temporal b...
Automatic Test Pattern Generation (ATPG) is an important task to ensure that a chip functions correc...
We propose a procedure for determining fault detection tests for single and multiple fault in combin...
Due to the character of the original source materials and the nature of batch digitization, quality ...
Most existing path sensitizing algorithms are only available for flat, combinational designs. We pre...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Consideration was given to the problem of time verification of the combinational circuits, namely, t...
Test Pattern Generation (TPG) for sequential and/or 3-state circuits involves two important aspects ...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
A powerful combinational path sensitization engine is required for the efficient implementation of t...
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds...
[[abstract]]Automatic test pattern generation (ATPG) for path delay faults is an essential tool for ...
The new test pattern generation system for path delay faults in combinational logic circuits conside...
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability o...
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel tech...
Abstract—Increasing speed and decreasing gate sizes make it necessary to test the correct temporal b...
Automatic Test Pattern Generation (ATPG) is an important task to ensure that a chip functions correc...
We propose a procedure for determining fault detection tests for single and multiple fault in combin...
Due to the character of the original source materials and the nature of batch digitization, quality ...
Most existing path sensitizing algorithms are only available for flat, combinational designs. We pre...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Consideration was given to the problem of time verification of the combinational circuits, namely, t...
Test Pattern Generation (TPG) for sequential and/or 3-state circuits involves two important aspects ...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...