A modular systolic architecture for delayed least mean squares adaptive filtering

Existing systolic architectures for DLMS adaptive filtering, delay the coefficient adaptation by (N-1) or N input sampling periods for a filter of order N. Further, these architectures enforce an output latency of the same amount, which translates to a tracking delay. Using an alternate systolization technique, this paper presents a systolic DLMS adaptive filter architecture in which the need for the tracking delay is eliminated and the amount by which the coefficient adaptation needs to be delayed-for systolization-is reduced by half. This would imply significantly improved convergence behavior over those of previously reported architectures. The architecture supports the same maximum sampling rate as the fastest such architecture reported so far, while using only half as many multiply-accumulate processor module