A VHDL study of area-power efficient delayed least-mean square filter

A typical architecture of the LMS algorithm suffers from large on-chip area as numerous adders, multipliers and delay registers are employed in its design. Due to the recursion, pipelining is not possible with LMS algorithm. Delayed LMS (DLMS) is an improvised form of LMS algorithm which allows pipelining of different tasks. An effective architecture of a novel partial product generator followed by an efficient adder is adopted here to implement a delayed LMS adaptive filter. This architecture helped in scaling down adaptation delay and on-chip area, which are the major drawbacks of conventional prototype. An error-computation block followed by a weight-update block is employed to obtain better performance. This new architecture was implemented in a hardware description language and all the design constraints of the digital filter were studied on different FPGA‟s