State assignment is a formidable task. As designs written in a hardware description language such as Esterel inherently carry more high level information that a register transfer level model, such information can be used to guide the encoding process. A question arises if the high level information alone is strong enough to suggest an efficient state assignment, allowing low-level details to be ignored. This report suggests that with Esterel's flexibility, most optimization potential is not within the high-level structure. It appears effective state assignment cannot rely solely on high level information
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis m...
Optimal state assignment is one of the most important problems in the automatic synthesis of sequent...
Abstract-In this paper, we address the problem of the state assign-ment for synchronous finite state...
We present a new procedure for automatically synthesizing controllers from high-level Esterel specif...
Producing efficient circuits from high-level language descriptions remains a problem. This paper pro...
Presenting designers with higher-level specification languages is one sure way to improve productivi...
this paper, we propose to use the Pure Esterel synchronization kernel of the Esterel language [4, 8...
The authors describe a state assignment algorithm for FSMs which produces an assignment of non-neces...
International audienceSeveral efficient compilation techniques have been recently proposed for the g...
Esterel and Safe State Machines (SSMs) are synchronous languages dedicated to the modeling of embedd...
This paper presents Metamorphosis 1 -- a novel technique for optimal state assignment targeting mu...
Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new impleme...
The fine-grained parallelism and the need for determinism are traditional issues in the design of re...
Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control uni...
An important step in the synthesis procedure for realizing a normal fundamental mode asynchronous se...
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis m...
Optimal state assignment is one of the most important problems in the automatic synthesis of sequent...
Abstract-In this paper, we address the problem of the state assign-ment for synchronous finite state...
We present a new procedure for automatically synthesizing controllers from high-level Esterel specif...
Producing efficient circuits from high-level language descriptions remains a problem. This paper pro...
Presenting designers with higher-level specification languages is one sure way to improve productivi...
this paper, we propose to use the Pure Esterel synchronization kernel of the Esterel language [4, 8...
The authors describe a state assignment algorithm for FSMs which produces an assignment of non-neces...
International audienceSeveral efficient compilation techniques have been recently proposed for the g...
Esterel and Safe State Machines (SSMs) are synchronous languages dedicated to the modeling of embedd...
This paper presents Metamorphosis 1 -- a novel technique for optimal state assignment targeting mu...
Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new impleme...
The fine-grained parallelism and the need for determinism are traditional issues in the design of re...
Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control uni...
An important step in the synthesis procedure for realizing a normal fundamental mode asynchronous se...
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis m...
Optimal state assignment is one of the most important problems in the automatic synthesis of sequent...
Abstract-In this paper, we address the problem of the state assign-ment for synchronous finite state...