Instruction Pipeline Efficient Mechanism with maximum hit ratio

To achieve highest performance in rapidly growing advancement in multi-core technology, there is need to minimize the large gap between faster processor speed and memory. It becomes more critical issue when branch occurs with penalty of cache miss. Many researchers proposed different branch prediction, instruction perfecting methods and algorithms but the CPU pipeline performance couldn’t be the maximal. A prototype model has been designed in this paper which has no prediction for branch and no chance of CPU core to be idle. Analysis is carried out on the benchmarks suite and Transactional Slice (TS) has been proposed in contrast with traditional delay slot and dynamic prediction fetch branch. In proposed mechanism hit rate will be maximal. Pin Tool is used to analyze the Transactional Slice with SPEC 2006 benchmark. DOI: http://dx.doi.org/10.11591/telkomnika.v11i11.3216