ABSTRACT GANDHI, JAYNEEL. FabFetch: A Synthesizable RTL Model of a Pipelined Instruction

High-performance superscalar processors examine a large pool of speculative instructions, called the dynamic instruction window, to exploit instruction-level parallelism (ILP). Scaling performance requires a larger and more accurate dynamic instruction window, which, in turn, requires a more accurate branch predictor. Achieving higher accuracy typically requires increasing the size of the branch predictor. Unfortunately, this may cause an increase in the processor's cycle time. A fast cycle time can be preserved by pipelining the branch prediction logic. This is not straightforward, however. The branch predictor uses the program counter (PC) of the current fetch block (among other context) to produce information that is needed to predict the PC of the next fetch block. This means that the inputs to the branch prediction logic depend on its outputs. This dependency loop within the branch prediction logic renders naive pipelining ineffective. Accordingly, if we want to use a larger branch predictor without increasing cycle time, then we need to apply sophisticated approaches to effectively pipeline the next PC loop. Several approaches to effectively pipeline the branch prediction logic hav