Software and Hardware for managing Scratch Pad Memory

This paper proposes a low-cost architecture to improve the management SPM (Scratch Pad Memory) in dynamic and multitasking modes. In this context, our management strategy SPM based on Programmable Automaton implemented in Xilinx Vertex-5 FPGA is entirely different from prior research works. SPM is generally managed by software (by a strong programming logic or by compilation). But our Programmable Automaton facilitates access to SPM in order to move code or data and liberates space in SPM. After this step, software takes over content management of SPM (what part of code or data should be placed in SPM, locates spaces of Heap and Stack). So the performance of the programs is actually improved thanks to minimization of the access latency at the DRAM (Dynamic Random Access Memory or Main Memory)