We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and performance by dynamically shifting the threshold voltage during operation. A small number of simple circuits are analyzed and it is demonstrated that subthreshold power can be reduced by a factor in excess of 103 for these examples
The colossal portion of power in CMOS circuits is consumed during switching which is termed as dynam...
In this paper, we propose new design techniques to reduce static dissipation by using transistors in...
The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS...
Abstract—Asynchronous spatial computing systems exhibit only localized communication, their overall ...
Low-power will be the primary focus of the semiconductor industry in the next decade. The threshold ...
As the scaling of CMOS technologies approaches the end of the roadmap, interests in alternative CMOS...
Abstract: Low power IC solutions are in great demand with the rapid advancement of handheld devices,...
In this work, we combine the advantages of silicon-on-insulator (SOI) technology with asynchronous d...
The need for low power dissipation in portable computing and wireless communication systems is makin...
This paper investigates with a mixed device/circuit simulation methodology the effectiveness of DG S...
Abstract—In this paper, the threshold voltage of fully depleted silicon on insulator device with geo...
International audienceThe historic trend in micro/nano-electronics these last 40 years has been to i...
Abstract: This paper presents a novel design methodology for ultralow power design (in bulk and doub...
Device power dissipation has grown exponentially due to the rapid transistor technology scaling and ...
This paper, for the first time, proposes and experimentally demonstrates an innovative design concep...
The colossal portion of power in CMOS circuits is consumed during switching which is termed as dynam...
In this paper, we propose new design techniques to reduce static dissipation by using transistors in...
The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS...
Abstract—Asynchronous spatial computing systems exhibit only localized communication, their overall ...
Low-power will be the primary focus of the semiconductor industry in the next decade. The threshold ...
As the scaling of CMOS technologies approaches the end of the roadmap, interests in alternative CMOS...
Abstract: Low power IC solutions are in great demand with the rapid advancement of handheld devices,...
In this work, we combine the advantages of silicon-on-insulator (SOI) technology with asynchronous d...
The need for low power dissipation in portable computing and wireless communication systems is makin...
This paper investigates with a mixed device/circuit simulation methodology the effectiveness of DG S...
Abstract—In this paper, the threshold voltage of fully depleted silicon on insulator device with geo...
International audienceThe historic trend in micro/nano-electronics these last 40 years has been to i...
Abstract: This paper presents a novel design methodology for ultralow power design (in bulk and doub...
Device power dissipation has grown exponentially due to the rapid transistor technology scaling and ...
This paper, for the first time, proposes and experimentally demonstrates an innovative design concep...
The colossal portion of power in CMOS circuits is consumed during switching which is termed as dynam...
In this paper, we propose new design techniques to reduce static dissipation by using transistors in...
The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS...
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