Add to ORKGAbstract: This paper presents a novel design methodology for ultralow power design (in bulk and double-gate SOI technology) using sub-threshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of MHz). It has been shown that a complete co-design at all levels of hierarchy (device, circuit and architecture) is necessary to reduce the overall power consumption. Simulation results of co-design on a five-tap FIR filter shows ~2.5x (for bulk) and ~3.8x (for SOI) improvement in throughput at iso-power compared to a conventional design. It has been further demonstrated that the double-gate SOI technology is better suited for sub-threshold operation
In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing ...
In this paper, it is attempted to analyze the power performances of few CMOS digital circuits such a...
Scaling of CMOS technology has enabled a phenomenal growth in computing capability throughout the la...
Abstract—This paper presents a novel design methodology for ultralow-power design using subthreshold...
Abstract: Low power IC solutions are in great demand with the rapid advancement of handheld devices,...
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various tec...
With aggressive scaling of device dimensions, threshold voltages and oxide-thicknesses, leakage-powe...
International audienceThe historic trend in micro/nano-electronics these last 40 years has been to i...
Low-power will be the primary focus of the semiconductor industry in the next decade. The threshold ...
AbstractThe leakage power dissipation has become one of the most challenging issues in low power VLS...
The need for low power dissipation in portable computing and wireless communication systems is makin...
An electronic system/appliance/portable device with high speed, low power, and feasible area has bec...
Technology scaling has taken circuit performance to unprecedented levels in the deep submicron regim...
In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be sim...
This dissertation has two new circuit level designs proposed. One a Dual edge triggered Near thresho...
In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing ...
In this paper, it is attempted to analyze the power performances of few CMOS digital circuits such a...
Scaling of CMOS technology has enabled a phenomenal growth in computing capability throughout the la...
Abstract—This paper presents a novel design methodology for ultralow-power design using subthreshold...
Abstract: Low power IC solutions are in great demand with the rapid advancement of handheld devices,...
Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various tec...
With aggressive scaling of device dimensions, threshold voltages and oxide-thicknesses, leakage-powe...
International audienceThe historic trend in micro/nano-electronics these last 40 years has been to i...
Low-power will be the primary focus of the semiconductor industry in the next decade. The threshold ...
AbstractThe leakage power dissipation has become one of the most challenging issues in low power VLS...
The need for low power dissipation in portable computing and wireless communication systems is makin...
An electronic system/appliance/portable device with high speed, low power, and feasible area has bec...
Technology scaling has taken circuit performance to unprecedented levels in the deep submicron regim...
In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be sim...
This dissertation has two new circuit level designs proposed. One a Dual edge triggered Near thresho...
In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing ...
In this paper, it is attempted to analyze the power performances of few CMOS digital circuits such a...
Scaling of CMOS technology has enabled a phenomenal growth in computing capability throughout the la...