EZW zerotree encoder architecture based on parallel processing of multi-bit-planes

Zerotree coding technique has been adopted by MPEG-4 for static texture coding. An EZW encoder architecture is proposed based on parallel processing of multi-bit-planes, and it can be used for real-time applications. Under the architecture, an effective preprocessor is designed to make each bit-plane independent for parallel processing on multi-bit-planes. In addition, zerotree coding on each bit-plane is divided into two stages based on the symbol definition and skip processing. The two stages are arranged in two tree-depth scans to avoid disorderly scan and processing. The architecture is tested on a system with an FPGA chip and it uses about 2500 logic cells. It is capable of encoding CIF images for real-time applications.EI03451-4554