An efficient parallel architecture for MPEG-4 zerotree encoder

This paper presents a novel parallel hardware architecture for MPEG-4 zerotree encoder. Under the architecture, a parallel processing of multi bit-planes is fulfilled through a preprocess unit and multi-encoding units. The preprocess unit consists of mainly a bit-not-and and a bit-or logic circuits. It ensures sufficiently that efficient encoding in each bit-plane is performed independently. Each encoding unit uses a fast technique to assign symbols by taking advantage of MPEG-4 zerotree coding symbol alphabet, and to select valid data to output using a ZTR address buffer.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000187118700115&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Computer Science, Artificial IntelligenceImaging Science & Photographic TechnologyCPCI-S(ISTP)